1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device having a capacitor and to a manufacturing method suitable for the semiconductor device.
2. Background Art
In recent years, in association with miniaturization of a semiconductor device, various approaches have been taken for ensuring a sufficient amount of capacitance in a cell area that has been scaled down for increasing storage capacity in a semiconductor device having a capacitor; e.g., DRAM (dynamic random access memory). For instance, there has been studied a method of using a high dielectric film, such as Ta2O5 (tantalum(V) oxide), BST (an abbreviation of BaxSr1 to x TiO3), and PZT (a ferroelectric formed from a solid solution consisting of a ferroelectric PbTiO3 and an antiferroelectric PbZrO3), as a dielectric film (also called a capacitive dielectric film) sandwiched between an upper electrode and a lower electrode of the capacitor.
The dielectric constant of a high dielectric film, such as Ta2O5, is about several times that of a conventional silicon oxynitride (SiON) film. Hence, so long as the high dielectric film is used as a capacitive dielectric film of a capacitor, there can be ensured sufficient capacitance required for accumulating electric charges in the capacitor even when the surface areas of electrodes of the capacitor become smaller in accordance with the area of a miniaturized cell. (C=∈S/d C: capacitance of a capacitor, ∈: dielectric constant, S: the area of the capacitor, and d: the thickness of the dielectric film)
Each of the high dielectric films is formed in an oxidizing atmosphere. When polysilicon is used as material for electrodes of a capacitor as conventionally, the surfaces of the electrodes are oxidized, resulting in formation of a silicon oxide film having a low dielectric constant and spreading of a depletion layer. For these reasons, even when a high dielectric film is consciously used as a capacitive dielectric film, a dielectric film is formed on the surface of electrodes as a result of oxidation. Accordingly, a capacitive dielectric film becomes thick correspondingly, resulting in a drop in capacitance of a capacitor.
Because of such a problem, there has been performed a study on a capacitor having an MIM (metal/insulator/metal) structure which uses, as a lower electrode, platinum (Pt) having strong acid resistance or ruthenium (Ru) whose metallic oxide (RuO2) has conductivity, rather than a conventional SIS (silicon/insulator/silicon) capacitor or a MIS (metal/insulator/semiconductor) capacitor.
A related-art method of manufacturing a semiconductor device having a capacitor will now be described by reference to FIGS. 9A through 9F and FIGS. 10A through 10C.
As shown in FIGS. 9A through 10C, a first interlayer insulating film 101 is formed on a silicon substrate 100. After a resist pattern 102 has been formed on the first interlayer insulating film 101, a first hole 103 is formed in the first interlayer insulating film 101 by means of dry etching (see FIG. 9A).
After removal of the resist pattern 102, the first hole 103 is filled with a first conductive film 104 (e.g., polycrystalline silicon, tungsten (W), or titanium nitride (TiN)) The first conductive film 104 is deposited also on the first interlayer insulating film 101 (see FIG. 9B).
Subsequently, the first conductive film 104 is removed from the first interlayer insulating film 101, by means of total etch-back or chemical-and-mechanical polishing (CMP). As a result, a plug 105 of first conductive film is formed within the first hole 103 (see FIG. 9C).
A second interlayer insulating film 106 is formed on the first interlayer insulating film 101 and on the plug 105 of first conductive film. After a resist pattern 107 has been formed on the second interlayer insulating film 106, a second hole 108 is formed in the second interlayer insulating film 106 by means of dry etching (see FIG. 9D). Subsequently, the resist pattern 107 is removed (see, FIG. 9E).
Barrier metal film 109; e.g., TiN (titanium nitride), and metal (e.g., Ru or Pt) film 110 which is to become a lower electrode (i.e., a storage node) of a capacitor are deposited, in this sequence, on the second interlayer insulating film 106 and on the second hole 108 (see FIG. 9F). Deposition of the barrier metal film 109 is intended for preventing reaction, which would otherwise be caused when the metal film 110, which is to become a lower electrode of a capacitor, comes into contact with the plug 105 of first conductive film, or for enhancing adhesion between the second interlayer insulating film 106 and the plug 105 of first conductive film.
Subsequently, the barrier metal film 109 and the metal film 110 which acts as a lower electrode of the capacitor are removed from the upper surface of the second interlayer insulating film 106 (see FIG. 10A), by means of total etch-back or CMP. Here, the second hole 108 maybe embedded with an organic substance, such as resist, before removal of the barrier metal film 109 and the metal film 110, thereby protecting the metal film 110 constituting the lower electrode of the capacitor. The organic substance may be removed after processing.
In order to increase the capacitance of a capacitor, a high dielectric film 111; e.g., Ta2O5, BST, or PZT, is deposited on the surface of second interlayer insulating film 106 and the metal film 110 constituting the lower electrode of the capacitor. Metal film (e.g., Ru, Pt, or Pt doped with iridium (Ir) for enhancing thermal stability) 112 which is to become an upper electrode of the capacitor (i.e., a cell plate) is deposited so as to fill the second hole 108, thus forming a resist pattern 113 (see FIG. 10B). The resist pattern 113 is removed after dry etching, thus forming a capacitor of MIM structure (see FIG. 10C).
At this time, when the metal film 112 constituting the upper electrode of the capacitor is formed from Ru, etching proceeds by means of reaction of Ru in O2 gas plasma (from Ru to RuO2(conductive) and RuO2 to RuO4 (volatile)). Alternatively, the metal film 112 may be etched by means of O2/Cl2 (oxygen/chlorine), CO (carbon monoxide), or CO/Cl2 gas.
When the metal film 112 constituting the upper electrode of the capacitor is formed from Pt, the metal film 112 is etched in Cl2/Ar (chlorine/argon) gas plasma (roughly corresponding to sputtering etching).
Even when there is formed a capacitor of MIM structure which uses a high dielectric film as a capacitive dielectric, larger variations due to process conditions arise in a high dielectric film, particularly when BST or PZT is used. In order to ensure dielectric strength, a high dielectric film must be thick. For this reason, difficulty is encountered in thinly forming a high dielectric film, thus hindering expectation of an upward leap in capacitance of a capacitor.
The invention described in Japanese Patent Application Laid-Open No. 220101/1999 is aimed at increasing the capacitance of a capacitor by means of forming lower electrodes in a columnar shape so as to increase the surface area of the capacitor. When lower electrodes are of columnar shape, the distance between lower electrodes is abruptly reduced in association with miniaturization of a semiconductor device. As a result, etch residues arise in a bottom, and hence a short circuit is apt to arise. Another problem is that columnar lower electrodes themselves become narrow and likely to fall. Thus, the invention yields a problem in terms of reliability of a semiconductor device.
The present invention has been conceived under such circumstances and is aimed at achieving an upward leap in the capacitance of a capacitor of MIM structure and further improvements in the reliability of a semiconductor device.
According to one aspect of the present invention, a semiconductor device has a capacitor of metal-insulator-metal structure, and the capacitor comprises an upper metal electrode, a lower metal electrode, and a capacitive dielectric film formed between the upper and lower electrodes. Further, the surface of the lower electrode is made rough.
According to another aspect of the present invention, a method of manufacturing a semiconductor device having a capacitor of metal-insulator-metal structure, the capacitor comprising an upper metal electrode, a lower metal electrode, and a capacitive dielectric film formed between the upper and lower metal electrodes, wherein the surface of the lower metal electrode is rough and the lower metal electrode is formed on a surface of a hole or trench formed in an interlayer insulating film, comprises the following steps. An interlayer insulating film is etched, thereby a hole or trench is formed firstly. A lower metal electrode is formed on the surface of the interlayer insulating film including the surface of the hole or trench formed therein secondly. An amorphous silicon film or amorphous metal silicide film is formed on the lower metal electrode thirdly. The amorphous silicon film or the amorphous metal silicide film is roughened, thereby rough polysilicon is formed fourthly. The lower metal electrode is etched while the rough polysilicon is taken as a mask, thereby the surface of the lower metal electrode is roughened fifthly. The rough polysilicon is removed sixthly. The lower metal electrode on the interlayer insulating film is removed such that a portion of the lower metal electrode remains on the surface of the hole or trench seventhly. A capacitive dielectric film is formed on the lower metal electrode eighthly. An upper metal electrode is formed on the capacitive dielectric film ninthly.
According to another aspect of the present invention, a method of manufacturing a semiconductor device having a capacitor comprising an upper metal electrode, a lower metal electrode, and a capacitive dielectric film formed between the upper and lower metal electrodes, wherein the surface of the lower metal electrode is rough and the lower metal electrode is formed on a surface of a hole or trench formed in an interlayer insulating film, comprises the following steps. An interlayer insulating film is etched, thereby a hole or trench is formed firstly. A lower metal electrode is formed in amorphous form on the interlayer insulating film including the surface of the hole or trench formed therein secondly. Nuclei of the same metal as that of the lower metal electrode are formed on the surface of the lower metal electrode and the surface of the lower metal electrode is roughened by means of heat treatment thirdly. The lower metal electrode on the interlayer insulating film is removed such that a portion of the lower metal electrode remains on the surface of the hole or trench fourthly. A capacitive dielectric film is formed on the lower metal electrode fifthly. An upper metal electrode is formed on the capacitive dielectric film sixthly.
According to the present invention, a semiconductor device includes a capacitor of metal-insulator-metal (MIM) structure, and the surface of a lower electrode of the capacitor is formed roughly (irregularly), and hence the surface area of the capacitor is increased. Thus, a large-capacitance capacitor of MIM structure can be formed.
In another aspect, the lower electrode is formed on the wall of a hole or trench of an interlayer insulating film. As a result, there can be prevented a problem of occurrence of a short circuit being liable to arise or a problem of a columnar lower electrode becoming liable to fall, which would otherwise be caused by etch residues formed on the bottom of a lower electrode when the lower electrode is formed into a columnar shape. Thus, a highly-reliable semiconductor device can be provided.
Other and further objects, features and advantages of the invention will appear more fully from the following description.